Synchronization in a packet-based communication system is typically achieved by exchanging timestamped packets between a master device and a slave device, both of which may be located at the edges of a packet network. The slave device typically implements a clock recovery algorithm that processes the timestamps to yield a signal that is used to control a local oscillator in the slave device.
Examples of known synchronization techniques of this type are disclosed in U.S. Patent Application Publication No. 2010/0158051, entitled “Method, Apparatus and System for Frequency Synchronization between Devices Communicating over a Packet Network,” Publication No. 2010/0158183, entitled “Frequency Synchronization Using First and Second Frequency Error Estimators,” and Publication No. 2010/0158181, entitled “Frequency Synchronization with Compensation of Phase Error Accumulation Responsive to a Detected Discontinuity,” all of which are commonly assigned herewith and incorporated by reference herein.
Packet delay variation (PDV) is a dominant source of noise in such packet-based communication systems. To filter this type of noise, many clock recovery algorithms select packets for processing based on a sample-minimum statistic of the network transit time. More specifically, a clock recovery algorithm typically groups arriving packets in non-overlapping windows and, for each window, selects the packet that had the shortest transit time through the network, with all other packets in the window being discarded. This operation corresponds to selectively downsampling the phase error signal by sample-minimum filtering. Although such sample-minimum filtering can be very effective in certain types of packet networks, there are many other networks and background traffic patterns for which sample-minimum filtering is far from optimal.